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Intel’s 14th Gen Meteor Lake-P Mobility CPUs With 14 Cores…

An entry within just the most current Linux boot log has disclosed a distinctive Intel 14th Gen Meteor Lake-P CPU that may provide as several as fourteen cores.

Intel’s 14th Gen Meteor Lake-P Mobility CPU Demonstrate Up In Linux Boot Logs With Up To 14 Cores

Uncovered by Coelacanth-Dream inside the Audio Open Firmware (SOF) venture inside of Github that was uploaded by Intel’s Fred Oh, there is a solitary Intel Meteor Lake-P CPU that is listed within the Meteor Lake-P (Family members: 0x6, Design: 0xAA, Stepping: 0x0) database. The CPU displays up as a ‘Genuine Intel (R) 0000’ model which is used to identify Engineering Samples (ES) and has a base clock of one.two GHz.

As detailed formerly, the Intel 14th Gen Meteor Lake-P CPU sample would not feature any help for AVX-512. The CPU sample was detected 3 instances in 3 distinct Bootlogs with two types of patterns, 1 with sixteen rational cores and the other with twenty sensible cores. To get to 16 cores, Intel has to offer a six P-Core and four E-Main configuration which signifies eight physical cores and 16 threads (reasonable). The max configuration is a 6 P-Core and 8 E-Main configuration which presents us 14 cores & 20 threads.

Intel Meteor Lake-P Mobility CPU With fourteen Cores Noticed In Linux Bootlog (Graphic Credits: Coelacanth-Aspiration):

From what I can notify, this is Intel testing out a extremely early Meteor Lake-P Mobility CPU sample which really should be clear from the decrease clock speeds. Intel’s 14th Gen Meteor Lake CPUs are predicted to start next 12 months and will rock two brand name new main architectures which ended up a short while ago confirmed as Redwood Cove for the P-Cores and Crestmont for the E-Cores.

There will be a list of other main IPs on board the quad-tiled chips these kinds of as the tGPU (Tiled-GPU) which will characteristic Arc-amount graphics architecture which is predicted to be fabricated on TSMC’s 3nm method node even though the CPU cores will rely on the Intel 4 (aka 5nm) procedure node and aid for up to LPDDR5X-7467 memory. The following is the whole listing of attributes to be anticipated from Intel’s 14th Gen loved ones:

13th Gen Meteor Lake Mobility CPU Lineup Anticipated Capabilities:

  • Triple-Hybrid CPU Architecture (P/E/LP-E Cores)
  • Brand name New Redwood Cove (P-Cores)
  • Model New Crestmont (E-Cores)
  • Up To fourteen Cores (6+eight) For H/P Sequence & Up To 12 Cores (four+eight) For U Series CPUs
  • Intel 4 Course of action Node For CPU, TSMC 3nm For tGPU
  • Intel Battlemage ‘Xe-LPG’ GPU With Up To 128 EUs
  • Up To LPDDR5X-7467 & DDR5-5200 Assist
  • Up To 96 GB DDR5 & sixty four GB LPDDR5X Capacities
  • Intel VPU For AI Inferencing With Atom Cores
  • x8 Gen 5 Lanes For Discrete GPU (Only H-Collection)
  • Triple x4 M.two Gen four SSD Aid
  • Four Thunderbolt 4 Ports


Once once more, the client launch schedule states a 2H 2023 release date even though the Corporate SIPP is prepared for 2023.

Intel Mobility CPU Lineup:

CPU Relatives Meteor Lake Raptor Lake Alder Lake
Method Node Intel four ‘7nm EUV’ Intel seven ’10nm ESF’ Intel seven ’10nm ESF’
CPU Architecture Hybrid (Triple-Core) Hybrid (Dual-Main) Hybrid (Dual-Core)
P-Main Architecture Redwood Cove Raptor Cove Golden Cove
E-Main Architecture Crestmont Gracemont Gracemont
Top Configuration 6+eight (H-Series) six+eight (H-Sequence) 6+eight (H-Series)
Max Cores / Threads fourteen/twenty 14/twenty fourteen/twenty
Prepared Lineup H/P/U Sequence H/P/U Sequence H/P/U Series
GPU Architecture Xe2 Battlemage ‘Xe-LPG’ Iris Xe (Gen 12) Iris Xe (Gen twelve)
GPU Execution Models 128 EUs (1024 Cores) ninety six EUs (768 Cores) 96 EUs (768 Cores)
Memory Assist DDR5-5600
LPDDR5X – 7400+
Memory Ability (Max) ninety six GB 64 GB 64 GB
Thunderbolt 4 Ports four two 2
WiFi Functionality WiFi 6E WiFi 6E WiFi 6E
TDP fifteen-45W fifteen-45W fifteen-45W
Launch 2H 2023 1H 2023 1H 2022

The write-up Intel’s 14th Gen Meteor Lake-P Mobility CPUs With 14 Cores Spotted by Hassan Mujtaba appeared initial on Wccftech.