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Intel’s 14th Gen Meteor Lake-P Mobility CPUs With 14 Cores…

An entry within just the hottest Linux boot log has exposed a distinctive Intel 14th Gen Meteor Lake-P CPU that may well supply as several as fourteen cores.

Intel’s 14th Gen Meteor Lake-P Mobility CPU Clearly show Up In Linux Boot Logs With Up To 14 Cores

Discovered by Coelacanth-Dream in the Sound Open Firmware (SOF) project in Github that was uploaded by Intel’s Fred Oh, there is a one Intel Meteor Lake-P CPU that is stated within the Meteor Lake-P (Spouse and children: 0x6, Design: 0xAA, Stepping: 0x0) databases. The CPU displays up as a ‘Genuine Intel (R) 0000’ product which is utilized to detect Engineering Samples (ES) and has a base clock of one.two GHz.

As in-depth formerly, the Intel 14th Gen Meteor Lake-P CPU sample will not aspect any assist for AVX-512. The CPU sample was detected 3 moments in a few distinct Bootlogs with two forms of styles, just one with sixteen rational cores and the other with twenty reasonable cores. To get to sixteen cores, Intel has to give a six P-Main and 4 E-Main configuration which implies eight physical cores and sixteen threads (logical). The max configuration is a 6 P-Main and eight E-Main configuration which presents us 14 cores & 20 threads.

Intel Meteor Lake-P Mobility CPU With fourteen Cores Noticed Inside of Linux Bootlog (Image Credits: Coelacanth-Aspiration):

From what I can inform, this is Intel screening out a pretty early Meteor Lake-P Mobility CPU sample which should really be evident from the decrease clock speeds. Intel’s 14th Gen Meteor Lake CPUs are envisioned to start up coming year and will rock two model new core architectures which were recently confirmed as Redwood Cove for the P-Cores and Crestmont for the E-Cores.

There will be a list of other core IPs on board the quad-tiled chips this sort of as the tGPU (Tiled-GPU) which will attribute Arc-amount graphics architecture which is envisioned to be fabricated on TSMC’s 3nm procedure node although the CPU cores will count on the Intel four (aka 5nm) approach node and guidance for up to LPDDR5X-7467 memory. The next is the entire list of capabilities to be envisioned from Intel’s 14th Gen relatives:

13th Gen Meteor Lake Mobility CPU Lineup Predicted Capabilities:

  • Triple-Hybrid CPU Architecture (P/E/LP-E Cores)
  • Brand name New Redwood Cove (P-Cores)
  • Brand name New Crestmont (E-Cores)
  • Up To fourteen Cores (6+eight) For H/P Collection & Up To twelve Cores (four+eight) For U Sequence CPUs
  • Intel four Method Node For CPU, TSMC 3nm For tGPU
  • Intel Battlemage ‘Xe-LPG’ GPU With Up To 128 EUs
  • Up To LPDDR5X-7467 & DDR5-5200 Guidance
  • Up To ninety six GB DDR5 & sixty four GB LPDDR5X Capacities
  • Intel VPU For AI Inferencing With Atom Cores
  • x8 Gen 5 Lanes For Discrete GPU (Only H-Collection)
  • Triple x4 M.2 Gen four SSD Support
  • Four Thunderbolt 4 Ports


After yet again, the buyer launch agenda states a 2H 2023 release day even though the Corporate SIPP is prepared for 2023.

Intel Mobility CPU Lineup:

CPU Spouse and children Meteor Lake Raptor Lake Alder Lake
Process Node Intel four ‘7nm EUV’ Intel seven ’10nm ESF’ Intel seven ’10nm ESF’
CPU Architecture Hybrid (Triple-Core) Hybrid (Dual-Core) Hybrid (Dual-Main)
P-Main Architecture Redwood Cove Raptor Cove Golden Cove
E-Main Architecture Crestmont Gracemont Gracemont
Leading Configuration 6+8 (H-Collection) six+8 (H-Series) 6+8 (H-Collection)
Max Cores / Threads 14/20 14/twenty 14/20
Prepared Lineup H/P/U Series H/P/U Collection H/P/U Collection
GPU Architecture Xe2 Battlemage ‘Xe-LPG’ Iris Xe (Gen twelve) Iris Xe (Gen twelve)
GPU Execution Models 128 EUs (1024 Cores) ninety six EUs (768 Cores) ninety six EUs (768 Cores)
Memory Assistance DDR5-5600
LPDDR5X – 7400+
Memory Ability (Max) 96 GB 64 GB 64 GB
Thunderbolt four Ports 4 two two
WiFi Ability WiFi 6E WiFi 6E WiFi 6E
TDP fifteen-45W fifteen-45W 15-45W
Launch 2H 2023 1H 2023 1H 2022

The submit Intel’s 14th Gen Meteor Lake-P Mobility CPUs With fourteen Cores Noticed by Hassan Mujtaba appeared initial on Wccftech.