Twitter person ExecutableFix positioned some thing known as “SH5”. SH5 is speculated to refer to the new AMD Instinct MI300 accelerator— which is a successor to MI200.
There’s a server socket known as “SH5” that features CPU with CPUID 0xA80F00… referred to as “MI300”
— ExecutableFix (@ExecuFix) September 16, 2021
Audience will remember that MI200 has nevertheless to launch. In actuality, the new MI200 is slated to be unveiled toward the conclusion of 2021. This is why the new socket leak is beneath major speculation.
Inside of the AMD Instinct MI200 is an Aldebaran GPU featuring two dies, a secondary and a major. It has two dies with each consisting of eight shader engines for a whole of 16 SE’s. Every single Shader Motor packs sixteen CUs with comprehensive-fee FP64, packed FP32 & a 2nd Technology Matrix Engine for FP16 & BF16 functions. Just about every die, as these, is composed of 128 compute units or 8192 stream processors. This rounds up to a total of 220 compute models or fourteen,080 stream processors for the total chip. The Aldebaran GPU is also run by a new XGMI interconnect. Each and every chiplet features a VCN 2.6 motor and the principal IO controller.
As for DRAM, AMD has absent with an 8-channel interface consisting of 1024-little bit interfaces for an 8192-bit vast bus interface. Each interface can support 2GB HBM2e DRAM modules. This must give us up to 16 GB of HBM2e memory potential for each stack and given that there are eight stacks in overall, the full amount of capability would be a whopping 128 GB. That is forty eight GB additional than the A100 which homes 80 GB HBM2e memory.
The MI300 is rumored to showcase 4 chipsets for GPUs, which occurs to be 2 times the total available for MI200. MI300 is not slated to launch for one more 12 months or for a longer period from other sources’ estimations.
ExecutableFix also states that SH5 variants could contain a Zen4 CPU chip in the exact same packaging, but once again less than speculation.
AMD discussed “Exascale APUs” in the whitepaper, “Structure and Evaluation of an APU for Exascale Computing.” In the paper, AMD hinted at a higher-performance APU design that “stacked HBM memory on prime of GPU chiplets which would be blended with CPU chiplets,” reports VideoCardz.
Two many years ago, Twitter person Komachi identified the initially hint of AMD MI200 Massive APU mode in reference to the MI200.
What is Massive APU Mode for MI200?
— 遠坂小町@Komachi (@KOMACHI_ENSAKA) December 26, 2019
With this new rumor, it could mean one thing additional alongside the strains of MCM GPUs attached to EPYC CPUs, processing info at the same time.
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