An alleged roadmap of AMD’s future-gen EPYC Server CPUs and Platform has been leaked out by AdoredTV. The roadmap lists impending server CPUs Genoa, Bergamo, Genoa-X, and Turin, alongside with a new platform known as SP6.
AMD’s Alleged EPYC Server CPU & Platform Roadmap Spills The Beans on Genoa-X, Turin, and SP6
We can not confirm the validity of the roadmap slides for this reason this publish is to be treated as a rumor but most of the aspects were being also reported previously by other leakers so it is really well worth sharing. Initial up, you can find the EPYC Server CPU roadmap for 2021-2023. The roadmap not only lists down EPYC server chips but also the respective platforms they are aimed at. AMD lately launched its remaining SP3 platform chips, the EPYC 7003X ‘Milan-X’ which are centered on the Zen 3 core architecture with 3D V-Cache.
EPYC Zen four(C) Expanded With Genoa, Bergamo, and Genoa-X
Going on, AMD wants to aim on the SP5 platform which is primarily based all around the LGA 6096 socket and will attribute at least two generations of processor lineups, Genoa and Bergamo. The AMD EPYC Genoa CPUs will function up to 96 Zen 4 cores in two hundred-400W SKUs while Bergamo will feature a whole of 128 Zen four cores in 320-400W SKUs. The SP5 platform is a superior-conclusion structure that features equally 1P & 2P support, up to 12-Channel DDR5 memory, up to a hundred and sixty PCIe Gen 5. lanes, and sixty four Lanes for CXL V1.one+, and up to 12 PCIe Gen 3. lanes.
The same roadmap also mentions Genoa-X, something that was also described by Moore’s Law is Dead in his video clip yesterday. The Genoa-X CPUs are anticipated to strike creation by finish of Q3 / early Q1 2023 and will launch about mid of 2023. They will characteristic a related style and design methodology as the Milan-X chips with 3D V-Cache as ‘Large L3’ is a highlighted attribute of the lineup. So in whole, SP5 will conclusion up with 3 EPYC families.
What is SP6? A Price tag-Optimized Variation of SP5 For Edge Servers
At the identical time, AMD is expected to introduce a new platform acknowledged as SP6 which will be a extra TCO-optimized offering for minimal-end servers. It will be a 1P alternative, giving 6-channel memory, 96 PCIe Gen five. lanes, 48 lanes for CXL V1.1+, and eight PCIe Gen three. lanes. The system will attribute Zen 4 EPYC CPUs but only the entry-level answers with up to 32 Zen four and up to sixty four Zen 4C cores. Their TDPs will array amongst 70-225W. So it looks like the SP6 platform is designed to support the entry degree variants of EPYC Genoa, Bergamo, and even Turin CPUs. It will concentration on Density & Perf/Watt optimizations for Edge / Telecommunication segment management.
In documentation identified by @Olrak (by way of Anandtech Forums), it looks like the SP6 socket is vastly related to the current SP3 socket so the packaging structure of the SP6 chips will be identical as opposed to existing EPYC CPUs too. They will never use the complete twelve-die layout as Bergamo does but rather adhere to an 8-die structure as the present sections. Although the socket seems the identical, the inner pin structure has been modified to LGA 4844 vs LGA 4096 (on SP3 sockets). Other measurements are the exact at 58.5 x seventy five.four.
Most of these products and solutions are envisioned to hit the marketplace in the 2nd half of 2022 and the first fifty percent of 2024. We can assume a formal announcement of the new roadmap by AMD before long and a achievable unveil for the duration of the Computex 2022 function which is slated in a several week’s time.
AMD EPYC CPU Family members:
|Family members Name||AMD EPYC Naples||AMD EPYC Rome||AMD EPYC Milan||AMD EPYC Milan-X||AMD EPYC Genoa||AMD EPYC Bergamo||AMD EPYC Turin||AMD EPYC Venice|
|Loved ones Branding||EPYC 7001||EPYC 7002||EPYC 7003||EPYC 7003X?||EPYC 7004?||EPYC 7005?||EPYC 7006?||EPYC 7007?|
|CPU Architecture||Zen one||Zen two||Zen three||Zen 3||Zen 4||Zen 4C||Zen 5||Zen 6?|
|Process Node||14nm GloFo||7nm TSMC||7nm TSMC||7nm TSMC||5nm TSMC||5nm TSMC||3nm TSMC?||TBD|
|Platform Title||SP3||SP3||SP3||SP3||SP5 / SP6||SP5 / SP6||SP5 / SP6||TBD|
|Socket||LGA 4094||LGA 4094||LGA 4094||LGA 4094||LGA 6096 (SP5)
LGA XXXX (SP6)
|LGA 6096 (SP5)
LGA XXXX (SP6)
|LGA 6096 (SP5)
LGA XXXX (SP6)
|Max Core Count||32||sixty four||sixty four||sixty four||96||128||256||384?|
|Max Thread Rely||64||128||128||128||192||256||512||768?|
|Max L3 Cache||64 MB||256 MB||256 MB||768 MB?||384 MB?||TBD||TBD||TBD|
|Chiplet Structure||four CCD’s (two CCX’s per CCD)||eight CCD’s (2 CCX’s for every CCD) + one IOD||eight CCD’s (1 CCX per CCD) + one IOD||8 CCD’s with 3D V-Cache (one CCX for each CCD) + 1 IOD||twelve CCD’s (one CCX for each CCD) + 1 IOD||12 CCD’s (1 CCX for every CCD) + 1 IOD||TBD||TBD|
|Memory Channels||eight Channel||8 Channel||8 Channel||8 Channel||twelve Channel (SP5)
|twelve Channel (SP5)
|12 Channel (SP5)
|PCIe Gen Assist||sixty four Gen 3||128 Gen four||128 Gen 4||128 Gen four||a hundred and sixty Gen five (SP5)
ninety six Gen 5 (SP6)
|one hundred sixty Gen 5 (SP5)
96 Gen five (SP6)
|TDP Array||200W||280W||280W||280W||200W (cTDP 400W) SP5
|320W (cTDP 400W) SP5
|480W (cTDP 600W)||TBD|
The article AMD EPYC Server Roadmap Leaks Out: EPYC Genoa-X With Zen four & 3D-V-Cache in 1H 2023, Genoa, Bergamo & Turin With SP6 Support by Hassan Mujtaba appeared to start with on Wccftech.